Embodiments of the present disclosure generally relate to semiconductor chips and semiconductor systems including the same.
As semiconductor systems are developed for high speed operations, it is becoming increasingly important to realize high data transmission rates between the semiconductor chips constituting a semiconductor system. In response, various pre-fetch schemes have been proposed for realizing high data transmission rates. The pre-fetch scheme may correspond to a design technique that latches data inputted in series and then outputs the latched data in parallel. The pre-fetch scheme may provide the high data transmission rates as well as the data having a high bandwidth. To obtain a parallel data, the clock signals having different phases, for example, multi-phase clock signals are required. The multi-phase clock signals may be generated in the semiconductor chips, and the multi-phase clock signals are used for inputting or outputting of the data.
In general, the multi-phase clock signals may be generated using an internal clock signal having a frequency, which is twice that of an external clock signal, and the internal clock signal may be generated using a phase locked loop (PLL) circuit.
However, the PLL circuit requires a large area in the circuit layout of the semiconductor chip and causes undesirably large current consumption. Thus, the semiconductor chip including the PLL circuit may suffer from high integration density and high power consumption. Further, the PLL circuit may require a relatively long locking time to generate the internal clock signal having a frequency which is twice that of the external clock signal.